Add Add Sum Shift left 1 Branch MemRead Instruction (6-0) MemtoReg Control ALUOP MemWrde ALUSrc RegWrite Instruction [19-15) Instruction [24-20)] Read address Read register 1 PC Read data 1 Instruction (31-0] Read register 2 Zero ALU ALU Instruction (11-7) Read data 2 Read data Address Instruction memory Write register result Write data Registers Write Data data memory Instruction (31-01 64 Imm ALU Gen control Instruction [30,14-12) During a particular clock cycle, consider the CPU shown in the drawing. Assume that the following initial data is present (all values are shown in decimal, DM is Data Memory): x8=72. x18=56. DM(64) = 48 During the cycle in question, assume that the following instruction is executed (the first column is the instruction's address: all values are shown in decimal): 51868 Id x8.8(x18) Write below the value of the bus L1 in decimal: 17 Write below the value of the bus L2 in decimal: L2 Write below the value of the bus L3 in decimal:

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Question
Add
Add Sum
1
Shift
left 1
Branch
MemRead
Instruction [6-0]
MemtoReg
ALUOP
Control
MemWrite
ALUSCC
RegWrite
L3
Instruction [19-15]
Read
address
Read
register 1
PC
Instruction (24-20]
Read
data 1
Instruction
[31-0]
Read
register 2
Zero
ALU ALU
Read
Instruction [11-7)
Read
data 2
Address
Write
result
data
Instruction
register
memory
Write
data Registers
Write Data
data memoryl
Instruction (31-0)
32
Imm
64
ALU
Gen
control
Instruction [30,14-12]
During a particular clock cycle, consider the CPU shown in the drawing. Assume that the following initial data is present (all values are shown in decimal, DM is Data Memory):
x8=72. x18=56, DM(64) =48
During the cycle in question, assume that the following instruction is executed (the first column is the instruction's address: all values are shown in decimal):
51868 Id x8.8(x18)
Write below the value of the bus L1 in decimal:
L1
Write below the value of the bus L2 in decimal:
L2
Write below the value of the bus L3 in decimal:
L3
Transcribed Image Text:Add Add Sum 1 Shift left 1 Branch MemRead Instruction [6-0] MemtoReg ALUOP Control MemWrite ALUSCC RegWrite L3 Instruction [19-15] Read address Read register 1 PC Instruction (24-20] Read data 1 Instruction [31-0] Read register 2 Zero ALU ALU Read Instruction [11-7) Read data 2 Address Write result data Instruction register memory Write data Registers Write Data data memoryl Instruction (31-0) 32 Imm 64 ALU Gen control Instruction [30,14-12] During a particular clock cycle, consider the CPU shown in the drawing. Assume that the following initial data is present (all values are shown in decimal, DM is Data Memory): x8=72. x18=56, DM(64) =48 During the cycle in question, assume that the following instruction is executed (the first column is the instruction's address: all values are shown in decimal): 51868 Id x8.8(x18) Write below the value of the bus L1 in decimal: L1 Write below the value of the bus L2 in decimal: L2 Write below the value of the bus L3 in decimal: L3
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